1. Technical Field
This invention relates in general to multiplexer circuits and, more particularly, to tree-type multiplexers having multiple selects wherein selector control signals are dispersed for high performance multiplexing, and to associated processes for configuring such multiplexers.
2. Description of the Prior Art
Multiplexers of different type are known in the art. One specific type of multiplexer is a tree arrangement such as disclosed in several earlier U.S. patents, e.g., U.S. Pat. No. 3,614,327, entitled "Data Multiplexer Using Tree Switching Configuration," and U.S. Pat. No. 3,654,394, entitled "Field Effect Transistor Switch, Particularly for Multiplexing." Another tree approach to multiplexing is to combine multiple data selects (such as the one of two select depicted in FIG. 1, having the logical function set forth in FIG. 2) in a layered configuration such as that depicted in FIG. 3. The multiplexer of FIG. 3 comprises a decoder wherein a particular data input from the thirty-two inputs X.sub.0 14 X.sub.31 is selected for output on line R by the signals appearing on control lines A.sub.0 -A.sub.4. This type of multiplexer has a significant advantage over other multiplex implementations in that the control lines A.sub.0 -A.sub.4 are much closer (in terms of logic depth) to the output and, therefore, provide a faster control path than other types of decode devices, such as a conventional AND function with decode control logic to drive the inputs. The AND function with decode control logic approach places loads on the control lines at a rate proportional to the number of data being selected.
The inherent drawback to tree-type multiplexing is that the approach also suffers from heavy loading conditions on the control lines. Loading within such structures typically increases at a rate proportional to the number of input data being selected. For example, in FIG. 3, control line A.sub.0 is loaded with one data selector(s), line A.sub.1 with two data selectors, line A.sub.2 with four data selectors, line A.sub.3 with eight data selectors, and line A.sub.4 with sixteen data selectors. This significantly higher load on control line A.sub.4 limits performance of the circuit. The disadvantage becomes more pronounced as the number of stages of multiplexed data selects increases, such as typically encountered with RAMs and ROMs. The present invention is designed to address this loading problem inherent in existing tree-type multiplexers.